Statistical Modeling of SOI Devices for the Low Power Electronics Program

This proposal by AET, Inc., directly addresses the computer aided-design system needs of the process and device development for the Low Power Electronics program. Besides the need for a commercial silicon-on-insulator (SOI) technology, significant reductions in process and device dimensions will be required. The combination of SOI material and small geometry devices will mean that wafer fab manufacturing variations will play a much larger role in determining circuit performance than in the past. For optimum performance, the designer must understand the relatiopnship between the process variations and the circuit performance. To address this problem, we propose to use the software technology called STADIUM which as been developed by Florida Institute of Technology under funding from SEMATECH. The thrust of this program is to perform research and development at AET, Inc., and Florida Institute of Technology aimed at transforming the STADIUM technology into a robust product for military and commerical dual use. The overall technical objective of the program is to establish the feasibility of statistical semicaonductor device simulation based on the methodology of design of experiments. In addition, we plan to investigate methodologies for developing statistical process and device models for SOI technologies which can be used to optimize processes and devices, and to estimate integrated circuit product yield. ANTICIPATED BENEFITS: This research will allow the commercilization of previous ARPA funded SEMATECH work and focus it on the Low Power Electronics program. The experience of AET's management team has the capability in a Phase II SBIR program to form the organization which will develop and support a robust software product for military and commercial dual use SOI integrated circuit development.