Radiation-Hardened Synchronous SRAM

Novel radiation-hardened synchronous pipelined multibank fault-tolerant static-random-access-memory (SRAM) will be developed. The SRAM will combine high speed performanceand radiation-hardness with high packing density, low power consumption andmanufacturability at reasonable costs. Unique circuits and circuit organization, i.e. self-compensating current-sense, voltage limiters, parameter-tracking references, self-adjustinglogic, shuffle, error corrector and fault-masking circuits, will contribute to narrow or close thespeed-gap between radiation hardened SRAMs and the digital-signal-processors DSPs. Fault-tolerance will be used only to the level that satisfies the requirements. In Phase I, thearchitecture and the key circuits and a test-chip concept will be developed, in Phase II acomplete SRAM will be designed, fabricated and evaluated, and in Phase III modified SRAMdesigns will be commercialized. The outcome of this effort will be key elements in futuredefense systems, commercial satellites, cosmic missions, nuclear weapons, power sources,propulsion devices and in other radiation hardened ambiences.The anticipated results of this research and development program can lead to abreakthrough in the implementation of an advanced national defense-system. Namely, theproposed SRAM is a key element that can satisfy the elevated requirements in operationalspeed and radiation hardness. The private industry would progress in obtaining high-reliabilityfast SRAMs for applications in extreme environments.