MICROELECTRONIC INFORMATION PROCESSING SYSTEMS.

EXPLORATORY RESEARCH IS PROPOSED TO DETERMINE THE IMPLEMENTATION FACTORS PARAMETERS FOR A NEW VLSI CELL INVOKING REDUNDANT NUMBER ARITHMETIC INSTEAD OF 1'S/2'S COMPLEMENT. A NARROW APPLICATION TOWARDS SIGNAL PROCESSING (MULTIPLY/ACCUMULATE INTENSIVE) SHALL DRIVE MINIMAL AREA AND SPEED DESIGNS. CARRY/BORROW FREE DESIGNS MAY GREATLY ENHANCE MODULAR FAULT-TOLERANT IMPLEMENTATIONS. FOR FURTHER FOCUS, THE EFFICIENT SIGNED BINARY NUMBER REPRESENTATION (SBNR) AS A TRIT-VALUED SUBSET OF GENERAL REDUNDANT NUMBER REPRESENTATIONS AFFORDS MORE IMPROVED AREA/SPEED FOM'S, THUS MAKING SUCH CELLS HIGHLY VLSI-REGULAR. THIS APPLICATION SPECIFIC STUDY SHALL IDENTIFY CRITICAL DESIGN PARAMETERS (MINIMAL LINE WIDTHS, FUNCTIONAL PARTITIONING, VIA'S # OF GATES, INTER/INTRACELL CONNECTIONS) TO AID THE DESIGN ENGINEER. FOCUS IS ON LOWER LEVELS OF COMPUTER ARCHITECTURE COUPLED TO TECHNOLOGY/IMPLEMENTATION ISSUES WHERE SIGNIFICANT DISCOVERIES MAY BE LEVERAGED INTO PRACTICAL SYSTOLIC ARRAYS EXCEEDING THE DESIGN PERFORMANCE OF GAPP AND DAP DEVICES WHILE ACHIEVING BREAKTHROUGHS IN MINIMAL CELL LAYOUTS.