ASSEMBLY OF A PROTOTYPE NEURAL ANALOG COMPUTER

THE OBJECTIVE OF THIS PROJECT IS THE DEVELOPMENT OF A PROTOTYPE GENERAL PURPOSE ANALOG NEURAL COMPUTER. THE MACHINE IS INTENDED FOR REAL TIME, REAL WORLD MASSIVELY PARALLEL COMPUTATIONS SUCH AS HIGH SPEED OPTICAL AND ACOUSTICAL PATTERN RECOGNITION, ROBOTICS AND THEE DEVELOPMENT OF SPECIAL PURPOSE NEURAL NETWORKS. THE COMPUTER WILL BE BUILT FROM VLSI MODULES DEVELOPED AT THE UNIVERSITY OF PENNSYLVANIA. IT IS SCALABLE TO ARBITRARY SIZE AND EVEN AT MODERATE SIZE, ITS EQUIVALENT COMPUTATIONAL POWER AND SPEED WOULD EXCEED BY MORE THAN 4 ORDERS OF MAGNITUDE THOSE OF ANY CURRENTLY AVAILABLE DIGITAL COMPUTER. THE RESEARCH WILL FORM THE BASIS FOR THE CONSTRUCTION OF A LARGE SCALE MACHINE AND THE DEVELOPMENT OF MILITARY AND COMMERCIAL APPLICTIONS OF SUCH MACHINES. THE MACHINE CONTAINS LARGE NUMBERS OF THE FOLLOWING SEPARATE ELEMENTS: NEURONS, SYNAPSES, AND ROUTING SWITCHES. ARRAYS OF THESE ELEMENTS ARE FABRICATED ON VLSI CHIPS THAT ARE MOUNTED ON PLANER CHIP CARRIERS EACH OF WHICH FORMS A SEPARATE MODULE. THE MODULES ARE CONNECTED DIRECTLY TO NEIGHBORING MODULES ON CIRCUIT BOARDS. NEURON RRAYS ARE ARRANGED IN ROWS AND COLUMNS AND ARE SURROUNDED BY SYNAPTIC AND ROUTING SWITCH ARRAYS. THE SWITCHES SELECT THE CONNECTIONS BETWEEN NEURONS. THE COMPUTER RUNS ENTIRELY IN ANALOG MODE. HOWEVER, CONNECTION ARCHITECTURES, SYNAPTIC GAINS AND TIME CONSTANTS, NEURON PARAMETERS SUCH AS THRESHOLDS AND TRANSFER CHARACTERISTICS ARE SET BY DIGITAL HOST COMPUTER EITHER DIRECTLY FROM THE KEYBOARD OR FROM STORED PROGRAMS. THE HOST COMPUTER ALSO MONITORS THE NETWORK PERFORMANCE BY OBTAINING MULTIPLEXED NEURON OUTPUTS THAT ARE THEN USED IN CONJUNCTION WITH LEARNING ALGORITHMS TO ADJUST NETWORK PERFORMANCE FOR PARTICULAR TASKS.