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Not Available Minimization of power consumption in electronics is a key requirement as spacecraft shrink in size. Semiconductor industry trends are leading power levels, lower, but not quickly enough to meet the needs of advanced missions or the new generation of broad-band communications satellites. Commercial electronics, while trending to lower power levels, do not include mechanisms to mitigate against the effects of space radiation. This is an increasingly severe problem in space as SEU effects are enhanced by smaller geometries. The goal of this SBIR is to demonstrate radiation tolerant, ultra low power VLSI combining breakthrough techniques in ultra low power with SEU mitigation techniques using commercial processes. This activity leverages on an ultra low power technology demonstration program (CULPRiT) that is being undertaken under sponsorship of DoD. CULPRiT will produce CMOS technology that operates at supply voltages near 0.25 volts. A 400 fold reduction in power levels is realized in comparing 5 and 0.25 volt processes in digital electronics. Specifically, this SBIR proposes to demonstrate a RT version of a ULP circuit combining ULP and RT technologies for space use.