A HIGH-SENSITIVE CCD READOUT TECHNIQUE

THE LOW NOISE PERFORMANCE OF CCD IMAGERS AND SIGNAL PROCESSING DEVICES IS PRESENTLY LIMITED BY THE PERFORMANCE OF THE ASSOCIATED CHARGE SENSING AMPLIFIERS. TYPICAL AMPLIFIERS WILL SHOW NOISE LEVELS OF 100 - 200 ELECTRONS/PACKET AND GAINS OF 1 - 5 MUV/ELECTRON. THE TRANSVERSE FLOATING-GATE FET PROPOSED HERE WILL CIRCUMVENT THE GAIN LIMITING STRAY CAPACITANCE AND PERMIT THE DEVELOPMENT OF AMPLIFIERS WITH 100 - 200 MUV/ELECTRON GAIN WITH NOISE LEVELS OF LESS THAN FIVE ELECTRONS. THE DESIGN OF THE DEVICE INVOLVES THE INTEGRATION OF PNP FET DIRECTLY ABOVE THE ACTIVE BURIED-CHANNEL REGION OF THE CCD. THE PNP DRAIN CURRENT TRAVELS ACROSS THE SURFACE OF THE CCD CHANNEL AND IS MODULATED BY PASSING BURIED-CHANNEL CCD CHARGE PACKETS UNDER THE FET. THE DOPING PROFILE OF THE DEVICE IS DESIGNED TO ISOLATE THE HOLES IN THE TRANSVERSE FET CURRENT FROM THE ELECTRONS IN BURIED-CHANNEL CCD CHARGE PACKETS. THE OPERATING FREQUENCY OF THE DEVICE IS LIMITED BY THE WIDTH OF THE CCD CHANNEL, BUT IS EXPECTED TO PROVIDE 1 - 10 MS/S OPERATION WITH 10K ELECTRON CHARGE CAPACITY.