VIOOL PROVIDES CONCURRENT ENGINEERING SUPPORT FOR BUILDING ELECTRONIC SYSTEMS

CONCURRENT ENGINEERING IS A CRUCIAL METHODOLOGY IN REDUCING DEVELOPMENT COST AND TIME OF HARDWARE AND ITS COMPLEMENTING SOFTWARE. TODAY NO TOOLS ARE AVAILABLE THAT CAN PROVIDE A TIGHT INTEGRATION OF HARDWARE AND SOFTWARE DEVELOPMENT (CO-DESIGN). ASC PROPOSES THE DEVELOPMENT OF VIOOL (VHDL INTERFACING OBJECT-ORIENTED LANGUAGES) AS A TOOL SUITE TO BOTH BRIDGE THE GAP BETWEEN WHAT IS NEEDED AND WHAT IS AVAILABLE, AND TO PROVIDE A TRANSFORMATION TO TRUE CONCURRENT ENGINEERING, INCLUDING RAPID PROTOTYPING, VIRTUAL PROTOTYPING, AND HARDWARE SOFTWARE CO-DESIGN. VIOOL USES EXISTING VHDL DESCRIPTIONS TO SAVE TIME AND MONEY, AND TRANSLATES THESE INTO C+++. THESE MODULES CAN BE TESTED TOGETHER. MOREOVER, COST AND PERFORMANCE INFORMATION OF THE COMPONENTS CAN BE TAKEN INTO ACCOUNT AS WELL, AND BASED ON CONSTRAINTS PROVIDED BY THE USER, A DESIGN CAN BE CREATED. THE GOAL IS TO HAVE A VHDL LIBRARY OF COMPONENTS, AND BASED ON THE NEEDS OF THE SOFTWARE, CREATE A HARDWARE DESIGN. THE PARTS THAT ARE NOT PUT INTO HARDWARE ARE TRANSLATED INTO OBJECT CODE FOR THE FINAL ARCHITECTURE.