AN OPTOELECTRONIC INTEGRATED CIRCUIT (OEIC) INDIUM GALIUM ARSENIDE RECEIVER ON A SILICON SUBSTRATE

THE RESEARCHERS PROPOSE TO DEVELOP A FULLY MONOLITHIC INTEGRATED RECEIVER CHIP FOR THE 1.3 AND 1.55 UM FIBER OPTIC WAVELENGTHS. THE CHIP WILL BE FABRICATED ON A SI SUBSTRATE SO THAT CONVENTIONAL BIPOLAR MOS-FET TECHNOLOGY CAN BE USED TO CONSTRUCT ALL OF THE PREAMPLIFIER ELECTRONICS. THEY WILL USE AN INNOVATIVE METHOD FOR THE GROWTH OF HIGHQUALITY INP AND RELATED COMPOUND EPITAXIAL LAYERS ON SILICON SUBSTRATES. THE HYDRIDE VPE TECHNIQUE WOULD BE USED TO COMPOSITIONALLY GRADE IN(X)GA(1-X)AS FILMS ON A COMMERCIALLY PURCHASED GAAS/SI SUBSTRATE FROM X=0 TO X=0.53. INP OR INGAAS(P) WOULD THEN BE DIRECTLY DEPOSITED ONTO THE LATTICE-MATCHED IN 53GA47AS. PERFORMANCE GOALS OF THE OEIC INCLUDE A 500 MB/S DATA RATE, -40 DBM SENSITIVITY AND EFFICIENT LIGHT DETECTION OUT TO 1.65 UM. DURING PHASE I, 75 UM DIAMETER PLANAR INGAAS PHOTODIODES, GROWN ON GAAS/SI SUBSTRATES, WILL BE FABRICATED, LIFETESTED AND DELIVERED AS PROTOTYPES ALONG WITH AN EPITAXIAL LAYER OF INP GROWN ON A SILICON SUBSTRATE.