SBIR/STTR Research Award
A SINGLE-CHIP SYMBOL/SIGNAL PROCESSOR FOR EMBEDDED EXPERT SYSTEMS
Award amount
$49,277Program and phase
SBIR · Phase IAward year
1988Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- Synapse Computer Services
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
A SINGLE CHIP INTEGRATED SYMBOLIC/NUMERIC PROCESSOR FOR EMBEDDED REAL-TIME EXPERT SYSTEMS WOULD GREATLY REDUCE THE COST AND DEVELOPMENT EFFORT FOR THE NEXT GENERATION OF DOD "BRILLANT" WEAPONS. MODERN "DIGITAL SIGNAL PROCESSING" SINGLE-CHIP COMPUTERS SUCH AS THE AT&T DSP32C AND THE TEXAS INSTRUMENTS 320C30 CAN ADDRESS MORE THAN 16 MEGABYTES OF MEMORY AND PROVIDE BETTER THAN 10 MIP AND 20 MFLOP (SINGLE PRECISION) PERFORMANCE WHICH IS ADEQUATE FOR MANY SIGNAL PROCESSING TASKS, AND WOULD SUPPORT A VERY FAST COMBINED SYMBOLIC/ SIGNAL PROCESSING CAPABILITY IF THE APPROPRIATE SOFTWARE WERE DEVELOPED. THE GOAL OF THIS PROJECT IS TO DEVELOP THE SOFTWARE ARCHITECTURE FOR A PORTABLE REAL-TIME EXECUTION ENVIRONMENT AND A PORTABLE CROSS-COMPILER FOR COMMON LISP FOR ONE OF THESE CHIPS AS A BASE FOR EMBEDDED REAL-TIME EXPERT SYSTEMS. THIS EXECUTION ENVIRONMENT FOR SINGLE-CHIP DIGITAL SIGNAL PROCESSING CHIPS WOULD HAVE THE FOLLOWING CHARACTERISTICS: PROGRAMMED IN STANDARD, PORTABLE COMMON LISP (VERY LITTLE ASSEMBLY LANGUAGE); COMPLETE REAL-TIME OPERATING SYSTEM WHICH OPERATES ON THE "BARE CHIP" (NO OTHER OPERATING SYSTEM); HIGH PERFORMANCE INTEGER AND FLOATING POINT PERFORMANCE FOR SIGNAL AND IMAGE PROCESSING; HIGH PERFORMANCE I/O; VERY LOW MAXIMUM INTERRUPT LATENCY (I.E., "REAL-TIME" GARBAGE COLLECTOR); EXTENSIONS FOR PARALLELISM THROUGH COOPERATIVE EXECUTION OF MULTIPLE SINGLE-CHIP PROCESSORS, AND PROGRAMMED USING STANDARD WORKSTATIONS AND PERSONAL COMPUTERS.
Technology keywords
Not reported