SBIR/STTR Research Award

Fast Matching for Sensor Data Exploitation Using FPGA

Award identifier 25b52269608b3fe063d6a70bda495ea029285bad8c85bca3fd92a37412c45cdaAwarding agency Department of Defense · Air Force

Award amount

$97,134

Program and phase

SBIR · Phase I

Award year

2001

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
BJ INFORMATION TECHNOLOGIES LLC
Proposal award date
Not reported
Contract end date
Not reported
UEI
Not reported
Solicitation number
Not reported
Topic code
Not reported

Research abstract

This proposal addresses the need to improve automatic change detection and pattern recognition in surveillance/reconnaissance systems. In those applications, large amounts of data are generated and must be stored and processed for each scene, which makesreal-time decision making a growing challenge. In the proposed Phase I project, we will study target matching algorithms which reduce the processing time. Another problem, which would be encountered in an operational imaging system, is the issue ofsignal processing hardware. The algorithms, to be studied in the proposed project, are insensitive to scale and rotation of the target in the image. The methods used in these algorithms are based on wavelet theory and genetic search paradigms. Thehardware is a compact FPGA design with externally linked memory. In the Phase II project, we will fabricate a breadboard imaging system using the algorithms and the hardware design developed and evaluated in Phase I.FPGA based integrated sensor and signalprocessing for high-speed detection and identification of targets.

Technology keywords

Not reported

Agency intelligence

Department of Defense

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