SBIR/STTR Research Award
Asynchronous Techniques for Noise Tolerant Nanoelectronics
Award amount
$96,266Program and phase
SBIR · Phase IAward year
2003Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Advanced Research Projects Agency
- Recipient company
- SITUS LOGIC
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
As progress in deep submicron technology exacerbates issues of clockdistribution, power consumption, control and estimation of delays, and noiseimmunity and tolerance, asynchronous techniques are becoming more and moreattractive.The design of an asynchronous MIPS microprocessor in 1998 and thecurrent design of an asynchronous 8051 microcontroller (both developed atCaltech in the proposer's laboratory) have demonstrated that asynchronoustechniques can produce circuits with high throughput and low powerconsumption, without sacrificing the robustness and reliability of a
Technology keywords
Not reported