RAPID, HIGHLY EFFICIENT SUBTRACTION CDNA CLONING METHOD

Not Available Theseus Logic has developed and demonstrated a proprietary new logic family, NULL Convention Logical (NCL), which integrates data transformation and control into a single expression thus producing inherently clockless, data driven, and effectively delay insensitive circuits and systems. Theseus proposes to take advantage of the NCL circuits developed both internally and in on-going programs such as Clockless Logic (DARPA contract DABT 63-96-C0057) and Cascade Processors (BMDO contract N00014-98-C-01) to demonstrate the advantages of an NCL design approach for combining computing speed with low power consumption. Specifically, Theseus proposes to use NCL components from these programs to build a DSP architecture testbed which will demonstrate the ability of an NCL architecture to provide the following benefits; Low Power - Data dependent processing. Gates not processing are quiescent and only consume leakage current. - Dynamic reduction of power supply voltage to match circuit speed to data rate. Plug and play system integration. - Collections of NCL circuits self synchronize at their highest common operating frequency. - NCL asynchronous interface circuitry for crossing multiple clock domains Reconfigurabilty and Adaptibility. - NCL circuits can be programmed into Xilinx FPGAs without the need for detailed timing analysis at the chip or system level. BENEFITS: NCL produces circuits which are clockless, data driven and effectively delay insensitive. As a result