Electronic Packaging Using Chip-on-Substrate Hermetic Coatings

The proposed innovation is to develop thin inorganic barrier coatings to protect bare chip-on-substrate (COS) multichip modules in lieu of normally used heavy and bulky ceramic/metal cavity packages. Inorganic coatings will be deposited over assembled microcircuits precoated with stress-free, high-purity polymers, sealing them from external moisture and internal outgassing. Previous work involved plastic encapsulation alone or inorganic coatings followed by plastic encapsulation. These approaches suffer from either non-hermeticity or exposure of the assembled circuit to high deposition temperatures. Reversing the sequence obviates these problems. This project will analyze and select compatible inorganic and organic coatings to reliably protect COS microelectronics from extreme terrestrial and space environments. Based on Phase I, experimental validation of the approach will be planned for Phase II. A 6-month effort consisting of assessment, evaluation and selection of a COS packaging approach for multichip modules and preliminary experimental studies are proposed. This technology will provide NASA and the commercial community with a weight/volume reduction of 50-80% for each module-important in achieving NASA's goal for the next generation of microspacecraft. There is also a potential reliability improvement (interconnections will be reduced by 50%) and cost reduction (eliminates large high-I/O count cavity packages).