SBIR/STTR Research Award
Bit Error Rate Tester Demonstration
Award amount
$83,253Program and phase
SBIR · Phase IAward year
1997Award details
- Awarding agency
- Department of Defense
- Branch
- Air Force
- Recipient company
- Terabit Technology, Inc.
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
Terabit Technology proposes to research and develop the high speed electronics technology required to prototype and produce a 25 Gbit/s bit error rate tester (BERT). Critical elements to be developed include the random word generator, multiplexer, amplifier, receiver, clock amplifier and recovery circuit, decision flip flop, demux and error counter. Packaging technology for 40 Gbit/s circuit will also be developed. After producing a prototype, we propose to further establish the commercial viability of this technology, and proceed to a rate of 40 Gbit/s.
Technology keywords
Not reported