SWITCH: Software Initiating Transition of Capability Hardware

Two types of cyber security flaws are responsible for the vast majority of all high-severity software vulnerabilities: memory safety failures and over-privilege. In our Phase I research on this topic, we developed methods to exploit those kinds of vulnerabilities in embedded systems. For Phase II, we propose to conduct additional research on preventing those vulnerabilities using new hardware enforcement methods.CHERI (Capability Hardware Enhanced RISC Instructions) extends conventional processor Instruction-Set Architectures with architectural capabilities to enable fine-grained memory protection and highly scalable software compartmentalization. When used correctly, the CHERI enhancements allow a computer's hardware to reliably prevent memory safety flaws and enforce least-privilege compartmentalization.  Most recently, ARM has teamed with Capabilities Limited to develop the Morello system, a multi-core computer system with CHERI enforcement mechanisms built in. However, developing software that uses the CHERI enforcement mechanisms remains a challenge, requiring highly-skilled developers with detailedCHERI experience.Here, we propose research that will mature the tool chain required to build CHERI-compatible software so that porting existing software is much easier, and developing new software is no harder than on other common computing platforms. This will lower the bar for adoption of memory-safe, capability-enforcing systems, catalyzing dramatic improvements in software security across a broad range of target markets.  At the same time, we will develop US-based expertise in the full CHERI ecosystem, supporting potential DoD and commercial applications that require US-based solutions. That expertise will also allow us to apply compartmentalization and memory safety methods to new CHERI-compatible hardware that may be developed, such as the expected RISC-V implementation that is already in progress.