SBIR/STTR Research Award
A GALLIUM ARSENIDE HETEROJUNCTION BIPOLAR TRANSISTOR FOR HIGH-SPEED ELECTRONIC INSTRUMENTATION
Award amount
$50,000Program and phase
SBIR · Phase IAward year
1992Award details
- Awarding agency
- Department of Energy
- Branch
- Not reported
- Recipient company
- Shen Associates
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
THE GALLIUM ARSENIDE HETEROJUNCTION BIPOLAR TRANSISTOR (GAAS HBT) IS A SUPERIOR ELECTRONIC COMPONENT FOR HIGH-SPEED AND HIGH PRECISION INSTRUMENTS BECAUSE OF GAAS HBT'S HIGH-SPEED, LOW NOISE NATURE. HIGH-SPEED DATA ACQUISITION SYSTEMS (E.G., FASTBUS, PARTICLE DETECTOR INSTRUMENT) USE FAIRLY COMPLEX INTERPOLATION SCHEMES TO COMPENSATE FOR THE LOW EDGE RATE SIGNAL THAT RESULTS FROM USING ELECTRONIC COMPONENTS THAT CANNOT RESPOND FAST ENOUGH. USE OF THE HIGH-SPEED GAAS HBT COMPONENTS IN A DATA ACQUISTION SYSTEM CAN ELIMINATE THE NEED TO USE COMPLEX INTERPOLATION SCHEMES, AND REDUCING SYSTEM COMPLEXITY AND IMPROVING SYSTEM PERFORMANCE. BECAUSE OF THE LOW NOISE NATURE OF GAAS HBT, AN INSTRUMENT USING GAAS HBT COMPONENTS CAN ALSO GREATLY REDUCE THE JITTER INTRODUCED IN SIGNAL PROCESSING AND SUBSTANTIALLY IMPROVE THE ACCURACY OF THE TIMING MEASUREMENTS. IN PHASE I OF THIS PROJECT, INNOVATIVE GAAS HBT DESIGN TECHNIQUES FOR CRITICAL ELECTRONIC COMPONENTS THAT ARE USED IN HIGH-SPEED, HIGH PERFORMANCE INSTRUMENTS ARE BEING DEVELOPED. SUCH COMPONENTS INCLUDE HIGH GAIN BROADBAND AMPLIFIERS, HIGH-SPEED COUNTERS, ENCODERS, AND ANALOG-TO-DIGITAL (A/D) CONVERTERS. THE INNOVATIVE DESIGN TECHNIQUES INCLUDE USE OF A PROPRIETARY ACTIVE LOAD IN THE HIGH GAIN BROADBAND AMPLIFIER AND USE OF AN ON-CHIP TRACK-AND-HOLD AMPLIFIER FOR THE A/D CONVERTER. THE FEASIBILITY OF HAVING A FREQUENCY SYNTHESIZER ON THE A/D CONVERTER CHIP IS BEING INVESTIGATED. THE SYNTHESIZER WILL PROVIDE A GIGAHERTZ INTERNAL CLOCK BY PHASE LOCKING TO AN EXTERNAL LOW FREQUENCY SYSTEM CLOCK. THIS WILL MINIMIZE THE EXTERNAL HIGH SPEED CLOCK ROUTING ON THE BOARD AND REDUCE THE SYSTEM COMPLEXITY AND OVERALL POWER CONSUMPTION. FINALLY, THE FEASIBILITY OF INTEGRATING SOME OF THESE COMPONENTS ON THE SAME CHIP IN ORDER TO FURTHER REDUCE POWER, NOISE, AND CLOCK FEED-THROUGH AS WELL AS IMPROVE PERFORMANCE IS BEING INVESTIGATED.
Technology keywords
Not reported