INTEGRATED SILICON-ON-INSULATOR MICROSTRIP DETECTORS

THIS PROJECT IS TO DEVELOP A HIGH ENERGY PARTICLE DETECTOR THAT INCORPORATES ONBOARD SIGNAL PROCESSING SUPPORT ELECTRONICS USING RADIATION-HARD, BOND-AND-ETCHBACK SILICON-ON-INSULATOR (BESOI) WAFER TECHNOLOGY. TAILORED FORUSE AT THE SUPERCONDUCTING SUPER COLLIDER (SSC), THIS DETECTOR DEVICE OFFERS IMPROVEMENTS IN SIZE, SPEED, POWER DISSIPATION, RELIABILITY, RADIATION RESISTANCE, AND COST WHEN COMPARED TO PRESENT DEVICES. THE PHASE I PROJECT WILL DEMONSTRATE THE FEASIBILITY OF INTEGRATING A MICROSTRIP DETECTOR DEVICE WITH A VERY LARGE SCALE INTEGRATED CIRCUIT ON A CUSTOM BESOI WAFER. PROCESS COMPATIBILITY WILL BE DEMONSTRATED BY COMPUTER SIMULATIONS. THE CUSTOM WAFER MATERIAL NECESSARY TO SUPPORT TESTING OF THE INTEGRATED DEVICE CONCEPT IS BEING FABRICATED. THESE WAFERS COMBINE THIN FILM (100) SILICON MATERIAL SUITABLE FOR METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR DEVICE FABRICATION WITH THE HIGH RESISTIVITY (111) MATERIAL NEEDED FOR THE DETECTORS. THESE COMPOSITE WAFERS ARE BEING CHARACTERIZED TO PROVIDE THE DATA NECESSARY TO OPTIMIZE THE BESOI PROCESS. DURING PHASE II, AN INTEGRATED MICROSTRIP DETECTORDEVICE PROTOTYPE THAT CAN BE USED BY THE SSC PROGRAM IS TO BE BUILT AND EVALUATED. THE WORK ON THIS PROJECT ALSO OFFERS POTENTIAL BEYOND THE PLANNED PHASE II BECAUSE THE TECHNOLOGIES THAT ARE DEVELOPED CAN SERVE AS THE STEPPING STONE TO ACHIEVE A VARIETY OF NEW TYPES OF INTEGRATED DETECTORS, INCLUDING TWO-DIMENSIONAL PIXEL TYPES OF ARRAYS WITH FAST READOUT CAPABILITIES.