Design Tools for Integrated Asynchronous Electronic Circuits

Through modern methodologies developed in the last decade, asynchronous self-timed logic has been demonstrated to be implementable in the large scale using VLSI CMOS technologies, while potentially providing significant advantages in terms of powerconsumption, high-performance, and ease of design and composition.Various research and academic institutions have put together the foundational works through research CAD tools and demonstration projects, ranging from microprocessors to application-specific VLSI systems. Despite these apparent progresses, there havebeen no perceived overwhelming advantages to asynchronous design to spur its widespread usage in addition to or in replacement of the well-honed synchronous methodologies.This Phase-I R&D proposal aims at putting together a development framework for asynchronous design, using a combination of existing industrial-standard language interfaces and CAD point tools, and synthesis packages for asynchronous logic developed by theasynchronous research community. The centerpiece of the present proposal is the use of a CMOS gate-array implementation substrate called Universal Logic Array (ULA). ULA allows the low-cost and fast-turnaround implementation of asynchronous logic in arobust and error-free way, unlike other approaches relying on ASIC or full custom designs. The key advantage of using a gate-array approach based on ULA is that it significant lowers the risks associated with designing using a new methodology, byproviding inexpensive manufacturing capability and fast turnaround. The goal of this R&D project is to encourage more usage of asynchronous logic methodology in various applications by non-expert designers. Once this barrier to entry has been removed, the advantages of asynchronous logic in term of power consumption,high-performance and ease of design will be fully demonstrated and appreciated, thus providing further impetus for widespread adoption of the methodology.