PROGRAMMABLE LINEAR DIGITAL BEAMFORMER

ADVANCES IN PROGRAMMABLE SIGNAL PROCESSING HARDWARE AND THE DEVELOPMENT OF TECHNIQUES FOR OPTIMIZING SIGNAL PROCESSING ALGORITHMS TO ACHIEVE HIGH PROCESSOR THROUGHPUT RATES HAVE MADE IT POSSIBLE TO DEVELOP A PROGRAMMABLE, LINEAR DIGITAL BEAMFORMER WITH THE FLEXIBILITYTO MEET A WIDE RANGE OF BEAMFORMING OBJECTIVES AT A REASONABLE COST. THE PROPOSAL PRESENTS AN APPROACH WHICH WOULD EMPLOY HIGH THROUGHPUT 32 BIT DIGITAL SIGNAL PROCESSORS, ARRAY PROCESSORS WITH UP TO 80 MFLOP EXECUTION RATES, A/D CONVERTERS WITH INTERNAL MULTIPLEXING, AND HIGH DENSITY, MULTI-PORT MEMORY CHIPS FOR PRODUCING A HIGH THROUGHPUT, YET PROGRAMMABLE, DIGITAL BEAMFORMER THAT IS VME BUS COMPATIBLE. TO AUGMENT THE HARDWARE, IT IS PROPOSED THAT THE LATEST TECHNIQUES DEVELOPED BY THE NAVY FOR MAXIMIZING HARDWARE THROUGHPUT ON ITS STANDARD REAL-TIME SIGNAL PROCESSORS BE APPLIED TO TAILOR THE SIGNAL PROCESSING ALGORITHMS TO THE HARDWARE. USING DATA FLOW PROGRAMMING TECHNIQUES AND SPECIAL PURPOSE ALGORITHMS, THE OVERHEAD ASSOCIATED WITH PROGRAMMABLE APPLICATIONS CAN BE MINIMIZED, THEREBY MAXIMIZING THE PROCESSING THROUGHPUT. PHASE I OF THIS PROJECT WOULD ESTABLISH THE PROCESSING REQUIREMENTS FOR THE BEAMFORMER AND MATCH THOSE REQUIREMENTS TO A HARDWARE ARCHITECTURE. PHASE II WOULD FABRICATE A PROTOTYPE OF THE PHASE I SPECIFIED BEAMFORMER.