A SYSTOLIC RAY TRACING PROCESSOR

THIS RESEARCH SEEKS TO DESIGN AN OPTIMAL SYSTOLIC PROCESSOR FOR THE NUMERICAL SOLUTION OF RAY TRACING ALGORITHMS. RAY TRACING REPRESENTS AN IMPORTANT FACET IN THE GRAPHICS WORLD BECAUSE IT CAN SIMULATE THE EFFECTS OF REFLECTION, REFRACTION, AND SHADOWS TO PRODUCE IMAGES THAT POSSESS A STRIKINGLY HIGH DEGREE OF REALISM, NOT OBTAINABLE BY OTHER METHODS. SINCE RAY TRACING IS VERY COMPUTATIONAL INTENSIVE,REQUIRING HUGE AMOUNTS OF CPU TIME EVEN ON A SUPERCOMPUTER SUCH AS THE CRAY X-MP, AND BECAUSE THESE ALGORITHMS ARE NOT GENERALLY AMENABLE TO VECTORIZATION, SYSTOLIC ARRAYS WOULD BE EXTREMELY EFFECTIVE IN IMPROVING THEIR EXECUTION. THE KEY STEPS IN THE OPTIMAL DESIGN PROCESS ARE: 1. IDENTIFICATION AND ADAPTATION OF RAY TRACING ALGORITHMS SUITABLE FOR SYSTOLIC IMPLEMENTATION. 2. IDENTIFICATION OF A BASIS OF SYSTOLIC MODULES FOR BUILDING A SYSTOLIC RAY TRACER. 3. SYNTHESIS OF THE FUNDAMENTAL SET OF SYSTOLIC ARRAY MODULES INTO A RAY TRACING PROCESSOR.