INTEGRATED DESIGN OF SMART PHASED ARRAY SYSTEMS

THE OBJECTIVE OF THIS PROJECT IS TO DEFINE THE DESIGN PRINCIPLES OF A SMART PHASED ARRAY RADAR SYSTEM WHICH INTEGRATES THE FOLLOWING FUNCTIONS (I) DIGITAL BEAMFORMING, (II) SELF-MONITORING OF ARRAY PERFORMANCE, (III) AUTOMATIC DETECTION AND CORRECTION OF COMMON AND CORRECTABLE ELEMENT FAILURES, AND (IV) RAPID (MICROSECOND) JAMMER NULLING. SELF-MONITORING AND FAILURE COMPENSATION WILL BE PERFORMED USING THE MEASURED DATA AND WILL NOT REQUIRE ANY EXTRA HARDWARE AT THE ARRAY ELEMENTS. RAPID JAMMER NULLING WILL BE PERFORMED USING FAST ALGORITHMS SUCH AS THE INVERTED GRAM SCHMIDT ORTHOGONALIZATION VIA THE HUNG-TURNER-KULLSTRAM ALGORITHM. THE ALGORITHMS WILL BE IMPLEMENTED USING A MULTIPROCESSOR NETWORK WITH THE BULK OF THE PROCESSING BEING PERFORMED AT THE ELEMENT LEVEL. THIS MULTIPROCESSOR NETWORK DESIGN WILL (I) ATTEMPT TO MINIMIZE INTRA PROCESSOR COMMUNICATIONS, AND (II) BE UPGRADED SO THAT IT CAN BE USED TO PERFORM MORE SOPHISTICATED TASKS SUCH AS TRACKING AND TARGET DISCRIMINATION.