SBIR/STTR Research Award
Design Tools for Reconfigurable High Performance Embedded Computing Architectures
Award amount
$98,198Program and phase
SBIR · Phase IAward year
2001Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Advanced Research Projects Agency
- Recipient company
- Management Communications & Control, I
- Proposal award date
- Not reported
- Contract end date
- Not reported
- UEI
- Not reported
- Solicitation number
- Not reported
- Topic code
- Not reported
Research abstract
Management Communications and Control, Inc. (MCCI) proposes development of design tools for development of high-performance embedded computing systems composed of malleable, reconfigurable architectures. The tools will provide a seamless path from importof algorithms from The MathWorks, Inc.'s tools to realization of systems design as compilable source code targeting programmable elements of the architecture and component architectures and component architecture behavior models specifying hardwareelements. An iterative design methodology supported by the tools will enable optimization of hardware and software architectures to meet space, weight, energy, performance, and time (SWEPT) design requirements. SWEPT requirements will be allocated toarchitecture elements in testable form as an integral part of the hardware/software codesign. Unit testing at the architecture element level using allocated SWEPT requirements and validation at every stage of system build processes will ensureconstruction of systems meeting their SWEPT requirements. Automation of detailed designs and code realizations will provide productivity enhancements that allow thorough examinations of algorithm and design trade space within realistic development budgetsand schedules.The design tools will empower expert design engineers. Productivity associated with developing high-performance embedded computing systems will increase by factors ranging from seven to nine. The productivity enhancement the tools providewill enable exhaustive trades of algorithm options, hardware architecture variations and software partitionings to optimize embedded system designs under SWEPT criteria within project budget and schedule constraints. The architecture design tools will beincorporated into our commercially available Autocoding Toolset.
Technology keywords
Not reported