A HARDWARE SCALABLE MICROPROCESSOR-BASED TESTBED FOR SYSTEM-LEVEL SIMULATION

THIS IS A PROPOSAL TO DESIGN AND IMPLEMENT AN EFFICIENT AND ECONOMICAL MICROPROCESSOR-BASED TESTBED FOR SYSTEM-LEVEL SIMULATION WHICH IS EASILY SCALABLE IN HARDWARE RESOURCES AND WHICH HAS A POWERFUL DEVELOPMENT ENVIRONMENT. THE PERFORMANCE TARGET OF THE TESTBED IS A TIME COMPRESSION TEN TIME GREATER THAN THAT FROM ONE OF THE CONSTITUENT PROCESSORS. THE SIMULATION TESTBED WILL BE DESIGNED TO EXECUTE ON A PARALLEL COMPUTING SYSTEM USING A NETWORKTYPE INTERCONNECTION NETWORK. THE CRUCIAL ELEMENT OF SIMULATION, EVENTS CHAIN MANAGEMENT, WILL BE DISTRIBUTED ACROSS MULTIPLE PROCESSORS. IN OUR APPROACH, DEVICES IN THE MODELED SYSTEM ARE ASSIGNED TO INDIVIDUAL PROCESSING ELEMENTS OF THE SIMULATOR HOST MACHINE AND THE INTERACTION AMONG THESE DEVICES IS REPRESENTED THROUGH SOME FORM OF MESSAGE PASSING SCHEME. DURING PHASE I OF THIS RESEARCH, WE HOPE TO ACHIEVE THE FOLLOWING OBJECTIVES TO DEMONSTRATE THE FEASIBILITY OF OUR APPROACH: TO DEVELOP AN EFFECTIVE CONCURRENCY CONTROL STRATEGY; TO DETERMINE AN APPROPRIATE HARDWARE HOST WITH A POWERFUL DEVELOPMENT ENVIRONMENT; AND TO DEVELOP A DESIGN FOR IMPLEMENTING THE TESTBED.