SBIR Phase II: Ge-Free Strained Silicon Via dTCE Bonding (Differential Thermal Coefficient of Expansion Bonding)

This Small Business Innovative Research Phase II project will develop a process that integrates wafer bonding technology with a novel straining process to create a new ultra fast silicon substrate: Strained-Silicon-On-Insulator (SSOI). This substrate can undergo normal IC fabrication and resulting circuits will be 30% faster at half the power required for comparative non-strained- SSOI architectures. The process is a direct approach and entirely surpasses the nearest competition as there is no germanium in any part of the processing. As a result the strained silicon is free from the high concentration of treading dislocations (>105 cm-2) always present when strained-silicon is grown on "strain-relaxed" silicon germanium virtual substrates. The silicon strained by the proposed method is maintained within its mechanically elastic region and thus is free from structural imperfections. The proposed method engages wafer bonding procedures already in place within the industry and modifies those processes to give a combined result of wafer bonding and SOI straining within a single step. The direct approach and single process makes the technique very inexpensive. The discipline evoked is fundamental surface science which involves investigation of both physical properties such as surface energies along with chemical aspects such as maintaining surface hydration and active surface species required for wafer bonding. Commercially, the substrates available via this effort will make possible ultra fast silicon electronics. The proposed process also allows for non-intrusive radiation-hardening, giving initial commercial outlet in the military sector. Further markets include mainstream silicon-based electronics; effectively new host materials with speeds more characteristic of materials such as gallium arsenide and most salient, very low power electronics.