SHIELDED HIGH TEMPERATURE SUPERCONDUCTOR INTERCONNECT TECHNOLOGY FOR PACKAGING HIGH SPEED CRYOELECTRONIC SYSTEMS

A PROTOTYPE HIGH TEMPERATURE SUPERCONDUCTOR (HTS) PACKAGING SYSTEM FOR HIGH SPEED CRYOELECTRONIC CIRCUITS WILL BE BUILT, TESTED, AND DELIVERED. THE CIRCUITS ARE EXPECTED TO BE HYBRIDS OF SEMICONDUCTOR AND SUPERCONDUCTOR COMPONENTS WHICH ARE INCORPORATED IN A PACKAGE WHICH WILL HAVE EXCEPTIONAL HIGH FREQUENCY PERFORMANCE, BE SECURE FROM HIGH FREQUENCY INTERFERENCE, AND PROVIDE MINIMUM ELECTROMAGNETIC RADIATION LEAKAGE. HTS TECHNOLOGY, BECAUSE OF THE EXCEPTIONALLY LOW SURFACE IMPEDANCE OF SUPERCONDUCTORS AND THE ABSENCE OF SKIN EFFECTS, CAN PROVIDE CRITICAL IMPROVEMENTS IN ELECTRONIC PACKAGING, ESPECIALLY IN THE 100 MHZ TO 10 GHZ RANGE. ALSO, CRYOGENIC OPERATION INCREASES CIRCUIT SPEEDS, IMPROVES SILICON THERMAL CONDUCTIVITY, AND LEADS TO A THOUSAND-FOLD DROP IN LEAKAGE CURRENTS. THE TENTATIVE PACKAGE DESIGN CALLS FOR AN APPROPRIATE SUBSTRATE WHICH IS BACKED BY A MULTI-LAYERED YBCO STRUCTURE - PATTERNED TO FORM SIGNAL INTERCONNECTS - AND INTO WHICH SILICON CHIPS ARE INSERTED. A POLYIMIDE STRIP, 1 MIL-THICK, IS PLACED ON TOP OF THE SIGNAL INTERCONNECTS AND TOPPED, IN TURN, WITH A HTS SHIELD. THE PHASE I OBJECTIVES ARE THE DESIGN OF AN OPTIMUM PACKAGE ARCHITECTURE AND THE DEMONSTRATION OF THE CRITICAL TECHNOLOGY REQUIRED FOR THE FABRICATION OF A MANUFACTURABLE MULTI-LAYER STRUCTURE COMPOSED OF APPROPRIATELY DIMENSIONED YBCO FILMS AND LOW DIELECTRIC CONSTANT INSULATORS. IT IS ANTICIPATED THAT A COMPLETE PROTOTYPE PACKAGE WILL BE CONSTRUCTED IN PHASE II.