Single Event Transient Soft Error Rate Prediction in Integrated Circuits

Single event transient (SET) effects on combinational logic have not been widelystudied because they have been deemed less important than logic circuits untilthe advent of deep sub-micron technologies. These new circuits tend to be moresensitive to SET because of the higher operating speeds and higher clock rates,and the smaller transistors themselves are more sensitive to radiation.AET, Inc. is developing a methodology to analyze the SET induced soft error ratein logic circuits. The approach is to model these SET induced soft error rates asfunctions of the design and technology of the integrated circuit. The models willbe incorporated into a software tool that will be utilized by development engineers. This tool will be complimentary to an AET tool presently in development aimed at calculating critical charge and total dose effects in integrated circuits.As a proof of concept, AET will design test structures to verify the validity ofthe approach and the AET software tool. Based on the results of this work, AETwill predict the primary factors contributing to SET susceptibility of the teststructures. Using the AET statistical analysis methodology, AET will develop apreliminary SET mitigation strategy.The primary benefit of the SET software tool will be to US Air Force advancedspace systems and commercial companies that supply IC's to these systems.Commercial satellite programs as well as military systems will utilize thistechnology to improve system performance and lower costs.