SBIR Phase I: Enhanced Parallelism for Faster Simulation and Validation of Integrated Circuits

The broader impact/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project will be in significant reduction of the time required to design complex integrated circuits (ICs) and accomplish comprehensive verification. ICs are integral part of modern electronic devices and play a critical role in determining device performance and cost. However, exponentially rising demand for better smartphones, tablets, laptops, etc., is forcing IC designers to include more features within a smaller format. These complex designs can take months for complete verification using the current state-of-the-art tools (simulators and emulators). Due to extremely high market competition, IC manufacturers are doing partial design verification and launching the products in the market. This is causing increased revocation of launched products, consumer dissatisfaction, loss of billions of dollars, and generation of e-waste. This work will enable comprehensive verification of ICs at a faster rate and lower cost thereby preventing massive economic losses and environmental pollution. This Small Business Innovation Research (SBIR) Phase I project aims to develop a technology that will provide IC design houses a distinctive advantage over the competition concerning time-to-market, risk, and remediation of post-silicon bugs, and design NRE (non-recurring engineering) by dramatically improving simulation performance. The innovation is based on successfully minimizing the limitations imposed by Amdahl’s law. To overcome Amdahl’s law, the company is developing an instruction-less, configurable computer architecture. It incorporates a bulk synchronous data flow architecture, using a proprietary data format and algorithm. The technology can in effect turn a single FPGA (field-programmable gate array) into hundreds of incredibly fast virtual processors that can concurrently solve product terms for equations at the speed of the processor-to-memory interface. The company has developed an initial virtual processor called the Boolean Processing Unit (BPU). The software converts the design from Verilog into a set of Sum-of-Product form Boolean equations, that the BPU can solve via targeting IC behavioral simulation computing, 30x faster than existing simulators. The innovation has the potential to provide emulator performance at simulator cost and features. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.