A metrology-based signoff tool for photonics integrated circuit design

The performance of silicon photonics (SiPh, nanophotonics) devices is very sensitive to manufacturing variations, due to both process bias and wall roughness that arise in fabrication. The goal of this project is to develop techniques and workflows that will allow device designers to take wall roughness into account during the design process, thus leading to devices that work at first fabrication. Silicon photonics holds out the promise of revolutionizing microelectronics. Photonics in general has already had major impact in information technology, as with photonics, information travels at the speed of light, and photonics transmission provides much higher bandwidth than other technologies, thus making for much wider as well as faster conduits for carrying information. However, silicon photonics is much more sensitive to manufacturing variations. Wall roughness can cause loss due to scattering of light out of the device. The goal of this project is to incorporate metrology and computation to provide technology for designing photonics devices while including manufacturing variations. This project will establish, through both metrology, modeling, and performance measurement, how roughness in different fabrication facilities can be characterized for use in device design. The result will be design tools usable by the photonics community that will reduce design iterations and result in reduced time to market for new devices.