SBIR Phase I: RISC-V and FPGA Pipeline-Coupled Heterogeneous Compute Microprocessor Architecture and Emulation Software Tools to Dramatically Improve CPU Performance

The broader impact of this Small Business Innovation Research (SBIR) Phase I project is to develop economical, green, and powerful computers for a hyperconnected, intelligent world. These scalable computers, from wearables to cloud-based systems, will revolutionize traditional computing, making artificial intelligence (AI), machine learning (ML), blockchain, cryptocurrency, and big data more affordable and sustainable. The ongoing data explosion requires smart, instantly-analyzed, handheld, battery-operated, content-driven, and voice-image recognized access to information. Users demand secure, private, upgradable, evolving, dependable, and economical connectivity anytime, anywhere. Battery-powered supercomputers in wearables and IoT devices will significantly enhance productivity, quality of life, and flexibility. These advanced computers will provide personalized features tailored to individual needs, ensuring families are safer, healthier, and more secure. Ubiquitous connectivity with voice-controlled access will enable new, unpredictable experiences, continuous learning, increased productivity, and improved lifestyles by balancing work and family time. Real-time generative AI prompts will assist us in daily life, remind us of forgotten tasks, teach us and our children, enhance healthcare, and suggest entertainment and food options. This Small Business Innovation Research (SBIR) Phase I project aims to revolutionize computer architecture by shifting from the traditional 60-year-old von-Neumann instruction computing to flexible content computing. This novel concept involves executing application software content as hardware images customized by the content to enhance computer metrics. Traditional computers rely on pre-defined instruction sets and hardware components, so that application software can be compiled into a sequence of selectable pre-defined hardware executables. This method is inefficient and consumes high energy, as instruction interpretation is more resource-intensive than the actual computational actions. The proposed innovation eliminates the dependency on instructions while retaining computational capabilities, thereby alleviating the data-bandwidth bottleneck. A novel hardware architecture augments a standard CPU pipeline with user-configurable hardware units. A novel compiler orchestration layer automatically generates a programmable hardware image that befits an identified software content. Flexible content computing is expected to significantly improve computer metrics, including: Super Scalar Instructions Per Cycle exceeding 30, performance increasing from 2 to 100, price reduction of 1/2 to 1/10, power reduction of 1/2 to 1/100, and code compaction by 1/3 to 2/3 times. These advancements promise to enhance computational efficiency and sustainability, setting a new standard in computer architecture. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.