SBIR/STTR Research Award

SBIR Phase I: A Mixed-Computation Neural Network Acceleration Stack for Edge Inference

Award identifier b3aea9f89d52646d5d609cb4088fcfce0b9fff95888d48dbbad11812dc658197Awarding agency National Science Foundation

Award amount

$274,915

Program and phase

SBIR · Phase I

Award year

2024

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
NOUVAI INC.
Proposal award date
2023-12-15
Contract end date
2024-12-31
UEI
QNDYZ7NR49S4
Solicitation number
NSF 22-551
Topic code
AI

Research abstract

The broader/commercial impact of this Small Business Innovation Research (SBIR) Phase I project is to improve the sustainability of artificial intelligence by reducing carbon emissions for training neural networks and performing inference at the edge. Additionally, the technology will spawn new applications and use cases for edge inference (including personal health, advanced data analytics, and informed decision-making), resulting in significant improvements in people's lives and well-being. The commercial potential is substantial (i.e., tens of billions of dollars annually), as are the potential economic benefits to US high-technology industries. This Small Business Innovation Research (SBIR) Phase I project sets out to develop a mixed-computation neural network acceleration stack utilizing optimally designed and provisioned hardware resources. This acceleration stack empowers a heterogeneous hardware realization of a neural network inference engine whereby computations required in various network layers may be done by using different number systems and different precision levels. The acceleration stack can thus achieve very high inference speed and energy efficiency while maintaining the inference accuracy compared to a homogeneous hardware realization of the network using 16-bit floating point computations. To support the design, optimization, and runtime efficiency of this edge inference accelerator, a full suite of software and design automation tools comprising a distiller for neural network architecture optimization and training, a logic synthesizer for generating optimized gate-level realization of very large and complex Boolean and multi-valued logic functions, a compiler for generating and scheduling control-flow and data path instructions that are executed on the target fabric, and a runtime system for orchestrating data movement will also be provided. The resulting edge inference accelerator will be deployable on resource-constrained, energy-limited, and cost-sensitive edge devices. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Technology keywords

Not reported

Agency intelligence

National Science Foundation

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