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Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Threat Reduction Agency
- Recipient company
- CFD Research Corporation
- Proposal award date
- 2023-11-02
- Contract end date
- 2024-06-02
- UEI
- V3KCP1HNFM33
- Solicitation number
- 22.4
- Topic code
- DTRA224-003
Research abstract
The demand for high performance electronic systems with small form factor has consistently been increasing the device density in integrated circuits (ICs). This trend is aided by the size reduction of semiconductor devices to nanometer levels. Such evolution of very large scale integration (VLSI) has resulted in the advent of System-on-a-Chip (SoC) and 3-Dimensional Integrated Circuit (3D IC). Multiple discrete ICs are packaged together either in a single chip (SoC) or a group of chips stacked on each other (3D IC). Such unique methodologies have significantly improved the capabilities of ICs allowing them to provide high speed, large storage and low power applications. However, radiation testing of such ICs has become increasingly complex, expensive and time consuming. The small form factor and high density integration of devices makes it difficult to test at a lower granularity which results in the reliance upon block and system level radiation testing. Such testing requires increased beam size to irradiate the entire assembly. Also, for 3D ICs high energy ions are needed to ensure penetration into radiation sensitive parts. Such radiation testing facilities that provide large beam and high energy ions are time consuming and expensive. Due to this only a few facilities are available in the United States and they are constantly overbooked. In order to deploy SoC and 3D IC based chips which are necessary to improve space and military applications, it is important to streamline and expedite the radiation testing process. In this work, we propose a methodology that utilizes spectroscopy and machine learning to efficiently provide radiation characterization and intelligent radiation hardness evaluation in SoC and 3D IC, that can help in reducing time and cost of radiation testing. This is achieved by extracting important information like system vulnerabilities including vulnerable regions and functions in SoC and 3D IC. In Phase I, we will design and develop this methodology to characterize and evaluate radiation effects in SoCs and extract data that can aid in reducing the time and cost of radiation testing. To achieve this goal we will design and employ ionizing radiation effects spectroscopy (IRES) experimentation to extract radiation characterization data and analyze it with machine learning based intelligent analysis that can identify vulnerable regions in SoC for selective testing. In Phase II, we will focus on 3D IC and adapt the proposed methodology to extract discrete and system level radiation characterization along with the packaging (both stacking and monolithic). This unique set of data will be subject to machine learning based intelligent analysis for radiation hardness evaluation which results in identification of vulnerabilities. These tasks will be accompanied with the prototyping and radiation testing of SoC studied in Phase I and the 3D IC studied in Phase II.
Technology keywords
Not reported
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Research funding history
947 SBIR/STTR records share this UEI (1987–2026). Reported award amounts total $350,893,199. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Health and Human Services, National Science Foundation, Department of Commerce, Department of Energy
Agency intelligence
Department of Defense
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