NANOPROTONIC DEVICES FOR >240× PERFORMANCE ANALOG AI HARDWARE

This proposal seeks the development of analog AI training processors with more than 240× performance to push the boundaries of AI without spending billions of dollars to train each new advanced model, or worse, burning down the entire planet. The building blocks of these architectures will be the novel class of nanoprotonic devices with ideal characteristics we will develop here, such that the resultant hardware can simultaneously have high-performance, high-energy efficiency, and high accuracy. Historically, the leading approach in this field has been to repurpose memory devices, that were originally designed for information storage purposes, which infamously fail to meet the requirements of deep learning, and information processing application. Instead, our proposed system prioritizes fast and efficient state transition, while also ensuring Si-integration compatibility for large-scale demonstrations. Previously, we demonstrated preliminary results on nanoprotonic programmable resistors that displayed state-of-the-art characteristics for analog deep learning. However, these devices could not enable large-scale demonstrations as their programming voltage was high and packaging properties were inadequate. We have identified the key bottlenecks and generated the proposed work plan to develop breakthrough material and interface innovations that will enable the immediate realization of large-scale integrated analog training processors. The resultant hardware will drastically improve the energy-efficiency of virtually all industries wherever complex AI applications are prominent, including healthcare, defense, banking, automotive, and retail.