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Award details
- Awarding agency
- National Aeronautics and Space Administration
- Branch
- Not reported
- Recipient company
- NIOBIUM MICROSYSTEMS INC
- Proposal award date
- 2023-07-28
- Contract end date
- 2025-07-27
- UEI
- LWWSLHU5YLE3
- Solicitation number
- SBIR_22_P2
- Topic code
- H6
Research abstract
The accelerator developed by Niobium Microsystems, Inc. (Niobium) is scalable in terms of parallelism and memory capacity, so that it can be targeted towards a variety of platforms, from small battery operated devices to large high-performance compute systems. It also has the ability to perform online learning when operating on neuromorphic workloads, drawing inspiration from the Hebbian learning paradigm. Additionally, the accelerator is designed as a memory-mapped peripheral of a larger heterogeneous System-on-Chip (SoC) and as such it can utilize external memory and implement arbitrarily sized Neural Networks (NNs) and even multiple NNs at the same time.Niobium is also prototyping several different approaches for incorporating radiation-tolerant features in the core by leveraging Niobiumrsquo;s novel digital circuit design flow, and incorporating magnetoresistive random-access memory (MRAM) where appropriate to harden the memory. As part of the Phase II effort, Niobium proposes to proceed with the implementation of the accelerator core with two additional innovations that are crucial to the NASA mission, but also have broader market potential in commercial and defense applications. Specifically, we plan to utilize Niobiumrsquo;s asynchronous circuit design techniques to (1) enable broad Dynamic Voltage Scaling (DVS) for enhanced protection against long-term radiation effects as well as potential improvements in energy efficiency, and (2) incorporate low-overhead radiation-tolerant circuits that protect against transient radiation effects, commonly referred to as Single-Event Transients (SETs), while minimizing the overhead in terms of power, performance and area. Lastly, as part of the implementation effort, Niobium intends to perform a quantitative tradeoff analysis between MRAM and conventional ECC-protected static random access memory (SRAM) with redundancy for the system-level cache of the accelerator.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
Research funding history
2 SBIR/STTR records share this UEI (2022–2023). Reported award amounts total $1,049,910. Reported amounts are not federal obligations.
Phases: Phase II, Phase I
Agencies: National Aeronautics and Space Administration
Agency intelligence
National Aeronautics and Space Administration
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