SBIR/STTR Research Award

Hardening Aircraft with FPGA's

Award identifier 3a787b65754b626e665232e2b5ae8026db52eb157d069cf4f7f11c5ab192a46fAwarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$2,983,130

Program and phase

SBIR · Phase II – Direct to Phase II

Award year

2022

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Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
WEB SENSING, LLC
Proposal award date
2022-09-28
Contract end date
2024-09-28
UEI
PRTXX18CC2N5
Solicitation number
22.4
Topic code
HR0011SB20224-06

Research abstract

We proposeĀto develop and demonstrate, on fieldable platforms such as the NAI 68ARM2 and 67G6 OpenVPX cards, a portfolio of FPGA capabilities for providing aircraft with resilience and security. These capabilities can be selectively combined by transition partners to meet cyber-defense requirements associated with DoD acquisition programs. Alternatively, the capabilities can be integrated into next generation systems, such as NAVAIRÆs Cyber Resilient Operating System (CROS).Ā To further this effort, we are actively supporting the porting of two formally verified hypervisors ¢ BHV and seL4 ¢ in collaboration with BedRock and DornerWorks respectively. Here we propose to adapt, enhance, and raise the Technology Readiness Level (TRL) our precision monitoring technology, developed under the DARPA AMP program, and our hidden-hardware approach to resilience and secure communication, developed under the DARPA SBIR and Air Force ICCyRIS programs. The objective of Year 1 is to integrate Encryption/Encapsulation, and Integrity Monitoring blocks into the FPGA portfolio. These tasks will involve adapting and enhancing existing FPGA blocks to operate on the 68ARM2 3U VPX architectureĀin the presence of either the Bedrock (BHV)Āor seL4 hypervisors.ĀĀ The objective of Year 2 is to develop MIL-STD-1553 Side-channel and Ethernet Backchannel capabilities, and integrate Refresh, Gold-standard Store, and Authentication blocks into the FPGA portfolio. The integration tasks will involve adapting and enhancing existing FPGA blocks to operate on the 68ARM2 architecture, in the presence of either the BHV or seL4 hypervisors. The objective of the Option year effort is to complete and support a technical handoff of designated elements of the FPGA portfolio, by raising their Transition Readiness Level to TRL 6 ¢ demonstrating their utility in a representative context.ĀĀThis effort may involve IV&V and/or the support for certification or accreditation through one of the standard paths: Federal Information Processing Standards (FIPS 140), Common Criteria (CC), Department of Defense in Information Network Approved Products List (DoDINAPL), Commercial Solutions for Classified (CSfC), or designated Authorization to Operate (ATO). Ā

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

8 SBIR/STTR records share this UEI (2016–2025). Reported award amounts total $8,830,970. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, Department of Energy

Agency intelligence

Department of Defense

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