SiC MOSFET WITH RADIATION-RESISTANT GATE OXIDE PERFORMANCE TO 600V

nbsp;Enhanced capabilities of Silicon Carbide (SiC) power semiconductor technology permit new ultra-high voltage and current applications and offer attractive options for power electronics in satellites, space stations and space exploration. However, the space environment has multiple radiation sources that interact with the SiC crystal and can damage the circuit. Studies show that when heavy ions impinge on an operating SiC power device, the device degradation may range from no discernable damage to increased leakage to catastrophic failure. In SiC MOSFET devices subjected to high-energy ion bombardment in the OFF-state, single-event burnout (SEB) and single-event gate rupture (SEGR) are two major failure types. Commercial SiC power devices have been observed to incur catastrophic failure at biases below 40% of their nominal blocking voltage, and irreversible degradation (SEGR) at biases well below 10% when exposed to ions with a Linear Energy Transfer (LETs) at 10 MeV-cm2/mg. Latent gate damage that precedes SEGR significantly limits the safe operation area of SiC MOSFETs for space applications. To avoid SEB failures, derating schemes are proposed like reducing the operating voltage to less than half its rated value. Similarly, to minimize SEGR, the operating voltage is reduced to less than one quarter of its rated value. Such de-rating penalty not only diminishes the SiC technology advantages of performance, cost and weight in space but may lead to costly field failures. SCDevice is developing a patented self-aligned device design for high-voltage SiC MOSFETs, with the goal of achieving reliable gate oxide performance up to 600V (state of the art MOSFET survives about 100V) for ion striking with LET=40 MeV-cm2/mg. Goal of Phase-I is to (a) Optimize device design for performance and (b) Demonstrate electric field across gate oxide below 4MV/cm for the ion strike at bias of 600V in the off-state.