SBIR/STTR Research Award
Automatic FPGA and IC Run-time Monitor (AFIRM)
Award amount
$167,382Program and phase
SBIR · Phase IAward year
2022Award details
- Awarding agency
- Department of Defense
- Branch
- Defense Microelectronics Activity
- Recipient company
- EDAPTIVE COMPUTING INC
- Proposal award date
- 2022-07-22
- Contract end date
- 2023-02-01
- UEI
- ULSZZUD8P7W7
- Solicitation number
- 22.1
- Topic code
- DMEA221-001
Research abstract
Develop a library of practical synthesizable register transfer logic (RTL) assertions (System Verilog is highly preferred), investigate limitations of synthesizable assertions in both integrated circuit (IC) and field programmable gate array (FPGA) design and design verification flows using already existing EDA platforms, and develop a methodology for synthesizable RTL assertions and error reporting. Identify robust test vehicles and implement synthesizable RTL assertions in both an FPGA and an IC.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- ARMED Phase II
- Synthesizable Register Transfer Logic (RTL) Assertions
- SEAMLESS: Secured and Assured Machine Learning Systems
- ARMED: Automatic Requirements Mapping to Architecture Diagrams
- Aeronautical Data Cyber Protection (ADEPT)
Research funding history
92 SBIR/STTR records share this UEI (1999–2023). Reported award amounts total $45,452,067. Reported amounts are not federal obligations.
Phases: Phase I, Phase II, Phase II – Direct to Phase II
Agencies: Department of Defense, National Aeronautics and Space Administration, National Science Foundation