SBIR Phase I:Security Evaluation Platform for Automating Inclusion of Hardware Security in Integrated Circuit Design

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to secure Integrated Circuit (IC) Intellectual Property (IP) against untrusted parties in the globalized IC supply chain.Outsourcing of IC foundries creates risks of IC reverse engineering, overproduction, theft, and even piracy. A promising method of achieving hardware IP security is by logically locking the functionality of a design by replacing a subset of the design components with programmable elements. The correct content of these elements forms the key for unlocking/activation of the design in a secure facility and/or via a secure protocol after manufacturing. A technical challenge in commercializing this technology is the long time period typically needed to assess the security of a locked design against state-of-the-art attack algorithms at the design phase. This project will address this technical challenge by developing an Artificial Intelligence (AI)-assisted design security analyzer tool to instantaneously provide an accurate attack runtime estimation on a locked design, significantly reducing the design time.This Small Business Innovation Research (SBIR) Phase I project will significantly shorten the time required to assess attack resiliency of an obfuscated (locked) Integrated Circuit (IC) design. Running the state-of-the-art Boolean Satisfiability solvers (SAT attack) on a state-of-the-art computer server to de-obfuscate a locked design can take time - ranging from days to months. Such a long security analysis time is prohibitive for deployment in the design process where iterative design optimizations are needed for making power, performance, area, and security (PPAS) trade-offs. This project aims to address this challenge by introducing a novel approach that will bring the security assessment time down to near zero using a machine-learning based model. Based on recent advancements in graph and geometric deep learning techniques, an innovative end-to-end security assessment framework is proposed that directly and losslessly ingests the original design as a graph-structured input, and then automatically learns the discriminative features that influence logic locking security. To support sufficient data for the proposed data-driven method, a logic locking macro-database will be developed that encompasses the required PPAS, attack and defense information.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.