SBIR/STTR Research Award

Dual Chipset ASIC and FPGA Approach for a Low Cost , Flexible, LPD Radio, Applique

Award identifier 9d77ddc956ebd2fcdacc4a5252d3d31dd468a8adbd17d40a4255af851e91299dAwarding agency Department of Defense · Army

Award amount

$199,952

Program and phase

SBIR · Phase I

Award year

2021

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Award details

Awarding agency
Department of Defense
Branch
Army
Recipient company
TERRY CONSULTANTS, INC.
Proposal award date
2021-09-13
Contract end date
2021-12-15
UEI
FH2MEMYMKLB3
Solicitation number
21.4
Topic code
A214-004

Research abstract

TCI seeks to develop and produce an innovative, low-cost dual chipset ASIC/FPGA SWAP optimized communications platform that operates as  Soldier borne electromagnetic warfare protection (EMWP)  module.  The comparative benefits of FPGA design versus ASIC designs are well-established in the semiconductor and manufacturer design industries. The pros for FPGA designs are extremely flexible platforms for designs that are software re-configurable and typically paired with high performance processor, industry standard I/O, and RAM. The cons for FPGA include high power consumption and high unit cost per design gate compared to ASIC designs. The pros for. ASIC designs are extreme efficiency, full customization of gates toward design objective which leas to superior power consumption, reduced area for the design and typically operational clock speed. Lastly, a couple orders of magnitude reduction in unit cost per design gate. The cons for ASIC Include no modifications to the design without spinning another chip, long lead times for tape-out for chip fabrication, In proposed design, we examine a single board design containing a high performance FPGA and custom ASIC EMWP Signal Encapsulation chip. Incorporating the industry-leading interface standard AMBA AHB bus interface will enable high speed interconnection between the FPGA subsystem and ASIC as well as components. The  ASIC EMWP is capable of direct sequence spreading (DSS) of binary data (0,1) or external digital IQ samples. The FPGA will be used to produce on-board digital IQ sample for lower rate source as a legacy radio, audio codec, and compressed video codec. The ASIC will generate a low probability of detection (LPD) payload by DSS the digital IQ samples or bits with a high speed featureless waveform running at either 20 MHz, 40 MHz or 80 MHz, depending on the register configuration.    The entire radio frame including training fields will be resilient to interference, electronic attack, and afforded a measure of  low probability of intercept (LPI) along with LPD. This  baseband LPB modem design will be paired with off-the-shelf wideband commercial transceivers and high-speed data converters (e.g. A/D and D/A). onto a single multi-layer board design. Custom lightweight ruggedized enclosures will enable the design to support a multitude of dual use applications such as expeditionary communications in the public safety sector, tactical small-medium size teams in military at the tactical edge, and large scale low powered device for Edge IoT applications.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

8 SBIR/STTR records share this UEI (2010–2023). Reported award amounts total $8,315,218. Reported amounts are not federal obligations.

Phases: Phase II, Phase I, Phase II – Direct to Phase II

Agencies: Department of Defense

Agency intelligence

Department of Defense

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