CMOS Integrated With Float Zone Pixel Sensor
Award amount
$1,099,793Program and phase
SBIR · Phase IIAward year
2021Award details
- Awarding agency
- Department of Energy
- Branch
- Not reported
- Recipient company
- NHANCED SEMICONDUCTORS, INC.
- Proposal award date
- 2021-05-03
- Contract end date
- 2023-05-02
- UEI
- LATHGF1NRTC1
- Solicitation number
- Not reported
- Topic code
- 32c
Research abstract
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Micro-Transfer-Printing Of Repeaters On Passive Interposer
- Energy-Efficient Reconfigurable Universal Accelerator Interconnect
- CMOS Integrated With Float Zone Pixel Sensor
- A New Cost-Effective Engineered Substrate
- 8k x 8k Delta Doped 3D Advanced Hybrid Detector Prototype For UV
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- 32c. Integrated Photonic Structures for Bunch Shaping in Structure Wakefield Accelerators
- Integrated high efficiency bunch shaping techniques for SWFA
- Integrated multiphysics design of high-power short-pulse lasers
- Integrated multiphysics design of high-power short-pulse lasers
Research funding history
21 SBIR/STTR records share this UEI (2008–2021). Reported award amounts total $9,451,098. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration