SBIR/STTR Research Award

STTR Phase I: A Software Platform for Assessment of Untrusted Electronics

Award identifier 433406d8012e9f3cb1b964be9cd0066a008b71a005150c7f4fc6b0d6f46d66e9Awarding agency National Science Foundation

Award amount

$256,000

Program and phase

STTR · Phase I

Award year

2021

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
SILICON ASSURANCE LLC
Proposal award date
2021-04-01
Contract end date
2022-03-31
UEI
HKMYQ28JLWV8
Solicitation number
Not reported
Topic code
S

Research abstract

The broader impact/commercial potential of this Small Business Technology Transfer (STTR) Phase I project is to address the security challenges that currently exist in integrated circuit (IC) design and the electronic design automation (EDA) software market. It will create a platform for ‘secure-by-design' of integrated circuits using untrusted third-party intellectual property blocks. It will provide a tool to semiconductor designers to automatically analyze security vulnerabilities and address them before fabrication. Such a capability will lead to security improvement of the fabricated chips and the systems they are integrated into, while also reducing the cost and time for secure system design through automation of vulnerability analysis and mitigation. The proposed toolset will address a critical technology gap in the semiconductor design and EDA marketplace. This Small Business Technology Transfer (STTR) Phase I project will develop a netlist assessment toolset which analyzes gate-level netlist of third-party integrated circuit (IC) design blocks used in modern system-on-chip (SoC) designs. The toolset converts the gate-level netlist to readable formats to support the existing security analysis tools in the electronic design automation (EDA) software market. During gate-level security analysis, this toolset will enable the detection of vulnerability for piracy, reverse engineering, as well as malicious logic in a design. To make the toolset market ready for our customers in the EDA and semiconductor industry, the SBIR/STTR Phase I project will mainly focus on scalability testing, interface design, analysis of security benefits, and performance improvement. Scalability testing of the toolset will be performed internally and with EDA industry customers to demonstrate the capability of the toolset in analyzing and converting the gate-level netlist of large scale SoCs. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

2 SBIR/STTR records share this UEI (2021–2023). Reported award amounts total $1,163,793. Reported amounts are not federal obligations.

Phases: Phase II, Phase I

Agencies: National Science Foundation

Agency intelligence

National Science Foundation

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