SBIR/STTR Research Award

SBIR Phase I: An Analog Hardware Accelerator for Power Systems Feasibility Studies

Award identifier 4ed1d7f14aa1bd5fca5a3ccffb28142cac642445300f856e19b0b0ddccdc9ce5Awarding agency National Science Foundation

Award amount

$305,000

Program and phase

SBIR · Phase I

Award year

2025

Explore This Research Award in CaptureIQ

Research the technology, evaluate the recipient and agency, identify related opportunities, and explore potential follow-on work with CaptureIQ.

Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
VELLEX COMPUTING INC
Proposal award date
2025-10-01
Contract end date
2026-09-30
UEI
GM9PU5JC3Z81
Solicitation number
NSF 24-582
Topic code
S

Research abstract

The broader/commercial impacts of this Small Business Innovation Research (SBIR) Phase I project are to enhance national energy security and maintain U.S. competitiveness in key technology areas including high-performance computing. Connecting new energy resources and loads, like advanced nuclear power plants and large-scale data centers, currently involves complex studies that can take years, creating a major bottleneck that increases costs and delays deployment. This project introduces a new type of hardware that can run these critical simulations thousands of times faster, reducing study times from months to days. This innovation will help utilities and energy developers bring new power projects online faster and at a lower cost. The technology provides a durable competitive advantage through its unique hardware design. The initial market will be utility companies and engineering firms, addressed through a cloud-based, pay-as-you-go service model. This Small Business Innovation Research (SBIR) Phase I project will address the computational limitations of simulating modern power systems. The slow speed of conventional digital software makes it difficult to analyze the complex dynamics of today’s electric grids. The primary research objective is to advance a proven analog computing architecture from a circuit board prototype to a scalable, integrated circuit. The proposed research involves the complete design and verification of a custom system-on-chip using a standard semiconductor process. This analog processor is designed to solve the full AC optimal power flow problem, a highly complex and nonlinear challenge. The project will also develop a software interface to allow the hardware to be controlled by existing industry-standard simulation tools. The anticipated technical result is a finalized, manufacturable chip design capable of simulating a standard 118-bus network with an accuracy of less than one percent error compared to traditional methods. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Technology keywords

Not reported

Agency intelligence

National Science Foundation

Back to SBIR/STTR Research Awards

Don't take our word for it. Ask AI about RFPCapture.

See what leading AI assistants have to say about RFPCapture and CaptureIQ.

Gemini opens without a prefilled question. The question is copied to your clipboard when the button works. You can also copy it here:

What is RFPCapture.com and its CaptureIQ platform from Smart Logic AI? How does it help federal contractors discover opportunities, evaluate bid/no-bid decisions, research government contracts, and prepare proposals? How does it compare with other federal capture platforms? Use independent sources where available.