SBIR/STTR Research Award

Scalable, High Power Cryocooler Controller

Award identifier 88e78c4a901f0575aa10d98fc57c496d7d916e3f48b37bdff4696ad890fd0f1dAwarding agency National Aeronautics and Space Administration

Award amount

$124,190

Program and phase

SBIR · Phase I

Award year

2020

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
IRIS TECHNOLOGY CORPORATION
Proposal award date
2020-08-28
Contract end date
2021-03-01
UEI
FZNZJD7228P5
Solicitation number
SBIR_20_P1
Topic code
S1

Research abstract

For this Small Business Innovation Research (SBIR) program Iris Technology proposes the Scalable, High Power Cryocooler Controller. The CCE will be optimized to provide power to large space cryocoolers capable of producing cooling of 0.3W at 10K and 0.2W at 4K. Iris is using the Lockheed Martin Space (LMS) Advanced Technology Center Mega Compressor as the target device.A number of innovative techniques to the CCE design are planned to achieve a target goal of 85% efficient production of 800 watts of cooler power. Two primary innovations are being applied to the power stages. The first is dynamic current balancing power slice architecture. This architecture uses a number of lower power slices that work together to provide the output power. The use of these slices reduce input and output capacitor requirements and allows the use of much smaller inductors, while synchronous operation increases efficiency, reduces power losses and eases thermal requirements, simplifying high power generation.The other innovation is the use of GaN FETs in the power stages in place of MOSFETs. The GaN FETs can switch more than 10 times as fast as MOSFETs, therefore capacitor and inductors values can be further reduced by another factor of 10 making the design even more space and power efficient.The objective is to develop a CCE design for high power, high efficiency cryocooler electronics compatible with the LM Mega Compressor. The design will include dynamic current balancing power slice architecture along with high speed GaN FETs to provide power and size efficiency. The CCE design goal is 85% power efficiency, with a low noise profile.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

26 SBIR/STTR records share this UEI (2006–2023). Reported award amounts total $12,441,596. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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