Fault Tolerant Parallel Processing for HPSC

NASA#39;s intention is that the new SOA for in space processing will be High Performance Spaceflight Computing (HPSC) Chiplet based. The HPSC formulation study identified several use cases including autonomy, human spaceflight, robotics, and science mission scenarios, which require significantly higher performance computing. In order to maximize performance to power ratio further efforts are required to Ramp;D a fault tolerant middleware for HPSC Chiplet Parallel Processing. This middleware needs to include Arm Cortex A53 general purpose register and Neon Single instruction Multiple Data (SIMD) optimized math and I/O kernels and library routines. During the Phase I effort, Antara will investigate and document a repeatable and deterministic methodology to identify and profile math and I/O kernel performance bottlenecks that significantly affect the performance of HPSC representative applications. Antara will establish criteria to prioritize the list of kernels for optimization and optimize several relevant kernels to show the feasibility of the methodology and scale potential. Additionally, Antara will perform systematic performance analysis and initial optimization of the math and I/O kernels and libraries that relate to HPC representative application SAR processing and report pre- and post-optimization performance indicators. Antara will bench-test its technology on relevant A53 based boards to establish and demonstrate deterministic performance to achieve TRL 4. The proposed innovation is significant and will enable the rapid development and infusion of anbsp;flight qualifiable Fault Tolerant Parallel Processing Packagenbsp;for the HPSC Chiplet.nbsp;Successful infusion of the cross-cutting innovation will enhance the HPSC Ecosystem and support major programs. The innovation will support potential near-term infusion targets such as Mars Fetch Rover, Lunar Gateway, SPLICE/Lunar Lander and the Moon to Mars campaign.