SBIR/STTR Research Award

System-on-Chip Virtual Isolated Network

Award identifier cb9adf5b708fedb365988fab847a08ab6334bdf58e5d5a1080a53f20456c7d4dAwarding agency Department of Defense · Defense Advanced Research Projects Agency

Award amount

$1,589,634

Program and phase

SBIR · Phase II

Award year

2020

Explore This Research Award in CaptureIQ

Research the technology, evaluate the recipient and agency, identify related opportunities, and explore potential follow-on work with CaptureIQ.

Award details

Awarding agency
Department of Defense
Branch
Defense Advanced Research Projects Agency
Recipient company
WEB SENSING, LLC
Proposal award date
2020-08-03
Contract end date
2022-11-03
UEI
PRTXX18CC2N5
Solicitation number
15.3
Topic code
OSD153-003

Research abstract

Under an original OSD Phase I SBIR effort, Web Sensing developed a strategic technology portfolio, with an associated market analysis, that isolated 4 related network security products: a Data Diode, Virtual Isolated Network (VIN), High-Assurance Guard (HAG), and Secure Programmable Logic Controller (Secure-PLC). These products all share the same technology base, leveraging building blocks defined through High-Level Synthesis (HLS) configured within Field Programmable Gate Arrays (FPGA) and System-on-Chip (SoC) Architectures. They provide a single-chip hardware base of trust that mitigates zero-day exploits, persistence, and reverse engineering. The initial Data Diode product was supported and developed under an OSD Phase II SBIR effort (AFRL Contract: FA8750-17-C-0267). It is now available commercially and marketed by MicroArx Corporation  in two different form factors -- a single diode and a high-density unit: the former protects individual elements of industrial plant; the latter provides secure and reliable file and database replication.  Under this DARPA Phase II Adoption, we are currently engaged in developing the VIN offering. This synthetic overlay network isolates designated traffic and allows it to be checked for validity through custom hardware parsers. In the first year of the effort we have already developed a prototype VIN PCB for Gigabit Ethernet and demonstrated how it can be used to provide validity checking of network traffic: This involved the realization of a bracket parser, in hardware, for individual Ethernet frames; encryption and the ability to handle multiple frames are ongoing activities. This proposal provides tasking for the second year of the effort, intended to generalize the range of applicability of the device and prepare it for market introduction.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

8 SBIR/STTR records share this UEI (2016–2025). Reported award amounts total $8,830,970. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, Department of Energy

Agency intelligence

Department of Defense

Back to SBIR/STTR Research Awards

Don't take our word for it. Ask AI about RFPCapture.

See what leading AI assistants have to say about RFPCapture and CaptureIQ.

Gemini opens without a prefilled question. The question is copied to your clipboard when the button works. You can also copy it here:

What is RFPCapture.com and its CaptureIQ platform from Smart Logic AI? How does it help federal contractors discover opportunities, evaluate bid/no-bid decisions, research government contracts, and prepare proposals? How does it compare with other federal capture platforms? Use independent sources where available.