SBIR/STTR Research Award
CTDSP Using Reconfigurable Devices
Award amount
$111,368Program and phase
SBIR · Phase IAward year
2020Award details
- Awarding agency
- Department of Defense
- Branch
- Army
- Recipient company
- GIRD SYSTEMS INC
- Proposal award date
- 2020-06-23
- Contract end date
- 2021-03-29
- UEI
- DJXELKH2ADS9
- Solicitation number
- 20.1
- Topic code
- A20-080
Research abstract
During this Phase I effort, GIRD will review their existing VHDL library for candidates for implementation as CTDSP components. On the implementation side, GIRD will address CTDSP FPGA implementation challenges including signal representation alternatives, continuous and discrete domain-crossing techniques, delay element mechanisms, and design tool idioms. These efforts will lead to the development of a CTDSP/clockless equivalent of selected GIRD library components and an initial design for a basic communication system component.
Technology keywords
Not reported
Other awards by this recipient
Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.
- Cue Aggregation Algorithms for Multi-Function Receivers
- Passive Sensing for Distributed Radars
- Passive Sensing for Distributed Radars
- Continuous-Time DSP Using Configurable Devices
- Domain Optimized Tactical Line of Sight Communications
Awards with the same topic code
Verified by an exact topic code match. This is not a text-similarity match.
- Continuous-Time Digital Signal Processing (CTDSP) Using Reconfigurable Devices
- Continuous-Time DSP Using Configurable Devices
- Continuous-Time Digital Signal Processing (DSP) Using Reconfigurable Devices
- Continuous-Time DSP Using Reconfigurable Devices
Research funding history
72 SBIR/STTR records share this UEI (2004–2025). Reported award amounts total $40,869,136. Reported amounts are not federal obligations.
Phases: Phase I, Phase II
Agencies: Department of Defense, Department of Commerce, Department of Agriculture