SBIR Phase I: Hardware Acceleration for Verifiable Delay Functions for use in Distributed Ledger Technology

The broader impact of this Small Business Innovation Research (SBIR) project is to design and develop a custom processor for performing cryptographic operations. This research will develop algorithms and implement them in hardware to improve their speed. The result of this research will be a design for a cryptographic accelerator that can be manufactured and used by the blockchain industry. These improvements will accelerate the practicality of blockchain for daily financial use, promoting low-cost open financial networks. These networks can reduce the cost of financial services and enable improved financial inclusion. This SBIR Phase I project proposes to increase the throughput, and reduce the cost, of blockchain consensus protocols. Through the use of a purpose-built cryptographic accelerator it will be possible to make many novel cryptographic techniques practical. These techniques include Verifiable Delay Functions (VDF), RSA Accumulators, and Succinct Non-Interactive Argument of Knowledge (SNARKs). In particular, this processor will focus on improving the efficiency of generating VDF proofs. VDFs and related cryptographic techniques hold great promise for improving the scalability and security of blockchain protocols, but are currently too slow on standard processors to provide the desired improvements. These techniques will enable the blockchain to be scaled to tens or even hundreds of times its current transaction throughput. Furthermore, these techniques will simultaneously reduce the computational and energy requirements of most modern blockchains dramatically. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.