Multi-Instruction Set Architecture (ISA) Processing with a Peripheral Component Interconnect express (PCIe)

Research has shown that Multiple Instruction Set Architecture (Multi-ISA) computing platforms can provide significant enhancements to performance, power consumption, and security. Yet, the Commercial off-the-shelf (COTS) marketplace has not developed such a platform where differing ISA processors exist as co-processors. Popcorn Linux addresses the software needs of such a platform, but suitable COTS hardware remains absent. Such hardware should be developed to realize Multi-ISA processing’s demonstrated benefits .PJR Corporation proposes to develop such a processing platform where an Advanced Reduced Instruction Computer (RISC) Machine (ARM) coprocessor is built on an Enterprise and Datacenter SSD (EDSSD) 1U form factor board (SFF-TA-1007 mechanical, SFF-TA-1009 signal definition) connected to an x86_64 host via PCIe. The proposed hardware is based on the Marvell OcteonTX SoC, which is composed of Cavium ThunderX processor cores, and allows for construction of a fully functional hardware proof of concept that can be assembled from COTS components. The hardware proof of concept will be used to evaluate the software development effort required to deploy a Multi-ISA operating system to the proposed hardware, allowing commencement and evaluation of this effort prior to incurring the acquisition costs of and lead time required for the proposed hardware.