Processor Redundancy Enabled Software Event Recovery with Voting (PRESERV)

New processor architectures, such as ARM and RISC-V have greatly improved SWAP-C for the computational power that they provide, especially when compared to the systems that are currently relied on for spacecraft requiring robust computer hardware. ARM has seen wide adoption in the consumer space due to its low cost and efficiency and RISC-V has the potential to enable the introduction of custom chip designs at a much smaller scale than what is currently possible, thus opening the door to the potential usage of specialized custom silicon for use on space missions. The low cost and high efficiency of these processors makes redundant architectures feasible. Using the NASA Core Flight System (cFS),nbsp; we develop a voting framework and couple it with a flight computer architecture that leverages redundant ARM commercial-off-the-shelf (COTS) systems on a chip (SOCs) or a custom redundant RISC-V processor to create the Processor Redundancy Enabled Software Event Recovery with Voting (PRESERV). As the interest in small spacecraft missions grows, including missions beyond earth orbit, there is a need for robust and capable computer platforms for these vehicles.nbsp; PRESERV meets these needs by combining the advantages of modern processor architectures and fault tolerance to give NASA new mission capabilities and provide a significant increase in robustness for low-cost spacecraft.