SBIR/STTR Research Award

Smart Memory Accelerator for Data Intensive and High Performance Computing Applications

Award identifier 8013f8329fad82a7e5f57ff9d71336fb28a9819209278612b1f6ac9c483f5065Awarding agency National Aeronautics and Space Administration

Award amount

$119,192

Program and phase

SBIR · Phase I

Award year

2019

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
SIMULTAC LLC
Proposal award date
2019-08-19
Contract end date
2020-02-19
UEI
RRM4L5HLWJ68
Solicitation number
SBIR_19_P1
Topic code
S5

Research abstract

This exploratory research will evaluate an alternative parallel non-von Neumann architecture class (Continuum Computer Architecture or CCA) in order to open new opportunities to extreme parallelism not available through conventional practices while mitigating current challenges to efficiency by means of fine grain hardware structures related to communication latency, synchronization overheads, adaptive contention avoidance, fault tolerance, and energy suppression. An advanced cellular architecture is to be derived such that the global emergent behavior will exhibit the properties of general-purpose parallel execution by means of local rules and high replication. Local rules will be based on a combination of dataflow and actors semantics with a reference tree implementation of a virtual global address space. This strategy reverses the common architecture priority of ALU utilization to stress memory bandwidth and data movement time and energy costs. Instead, ALU availability is emphasized. Beyond the local operation, global operation is guided by the experimental ParalleX execution model to govern resource management and task scheduling, and impose user-friendly programming model. Micro-benchmarks derived from computational kernels of existing applications will be applied to analysis of CCA behavior over a range of scientific computing algorithms (including climate, linear algebra, and graph problems). The proposed Phase I research is a stepping stone intended to inform the design and development of the future optimized custom silicon structures composing the Smart Memory Accelerators to be deployed in NASA data centers alongside the conventional supercomputing hardware. An important characteristic of CCA is the simplicity and uniformity of the computing structures that makes the CMOS implementation feasible to a small engineering team. If successful, this research will minimize the userrsquo;s time to solution, and increase the scale and complexity of executed problems.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

2 SBIR/STTR records share this UEI (2019–2020). Reported award amounts total $869,097. Reported amounts are not federal obligations.

Phases: Phase II, Phase I

Agencies: National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

Back to SBIR/STTR Research Awards

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