SBIR/STTR Research Award

Xen Project Hypervisor for the High Performance Space Computing Platform

Award identifier 9b97919ad56a91455f95db02a2a010c662b19dfc4d7d5fcd019b6bccd8b51d68Awarding agency National Aeronautics and Space Administration

Award amount

$124,846

Program and phase

SBIR · Phase I

Award year

2019

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
DORNERWORKS, LLC
Proposal award date
2019-08-19
Contract end date
2020-02-18
UEI
WB5DBBC8RES7
Solicitation number
SBIR_19_P1
Topic code
Z6

Research abstract

DornerWorks is seeking to enhance the capabilities and ecosystem of the open source Xen Project hypervisor, targeting full integration with the High Performance Space Computing (HPSC) platformrsquo;s High Performance Processing Subsystem (HPPS) through this project. There will be several tangible benefits stemming from this Phase I project.nbsp;This project will show the Xen Project hypervisor to be a viable, open source, bare metal, hypervisor solution for the HPSC. Embedded hypervisors have been ported to hardware similar to the HPSC-HPPS, like the Xilinx Zynq UltraScale+ MPSoC and the NXP i.MX 8, for products in several different commercial markets to:Help manage available processing power,Provide isolation between software components,Enable multiple operating systems running on the same processor, andMore easily support software redundancy.This project will also add capabilities and make improvements to the Xen Project hypervisor to better suit it for use with the HPSC hardware and software components. A gap analysis between the Xen Project hypervisorrsquo;s capabilities and HPSC requirements will have been performed, identifying remaining improvements or new feature to be implemented in Phase II. This project will also substantively improve the Xen ecosystem with regards to space programs and missions by adding Xen support of a real time operating system (RTOS), like RTEMS, on A53 processors. This will be of value to future programs targeting the HPSC, and of immediate value for programs currently developing software on similar hardware available today, such as the Xilinx MPSoC used on platforms like Innoflightrsquo;s CFC-400 Compact Hybrid Architecture for Multi-Parametric Sensing (CHAMPS) Flight Computer.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

23 SBIR/STTR records share this UEI (2011–2025). Reported award amounts total $11,505,684. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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